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introducing mapper

By breaking the mold for e-beam lithography, Mapper introduces the unique benefits of e-beam direct-write to regular semiconductor manufacturing. For decades e-beam systems have been the laboratories’ beloved workhorses, due to their high resolution and for the flexibility that comes with not having to create costly masks. Today however, by their single-beam nature, these traditional systems can’t scale up to series production: it may take days to expose a fully covered 300 mm wafer at nodes below 90 nm. By deploying up to 650,000 parallel beamlets, it takes only minutes to do the same with Mapper technology. Even at 28 nm. Even at full density.

The Mapper FLX series revolutionizes the use of e-beam lithography: on the one hand it is a perfect companion when researching device characteristics, prototyping new applications and doing specialized low volume applications. On the other hand it is a scalable manufacturing method, an enabler to step up to volume production. Producing thousands of wafers per month with fully customised e-beam layers in mix-and-match operation with optical lithography is now a viable solution.

mapper applications

High-resolution patterning without a mask enables a broad spectrum of new applications in 200 mm and 300 mm production lines. From making each chip on a wafer truly unique to making wafer-sized MEMS devices. From bringing sub-100 nm resolution into 200 mm fabs to introducing full-2D patterning at advanced nodes.

Chip view
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rf and 5g

Most mixed-signal devices are made in 200 mm lines where analog performance is uncompromised. However, advanced imaging beyond 90 nm is expensive and unwieldy at 200 mm, imposing a limit on the switching speed of the most critical bipolar devices, such as SiGe transistors. The FLX series brings 28 nm node imaging to 200 mm fabs, boosting fT and bandwidth for RF and 5G applications without having to resort to difficult tricks.

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iot security

In a world increasingly connected to the Internet new levels of security are needed to protect our privacy and infrastructure. Connected device functions in the Internet of Things (IoT) must be protected against a growing list of external threats. The value for attackers to break into these systems increases as the popularity of all kinds of connected devices soars. Per-IC and per-wafer diversification offer new protection schemes that are firmly rooted in hardware. Now you can diversify, in a controlled manner, individual microscopic features such as vertical interconnects, metal wires and gates. This renders the effort of physically attacking a single device futile.

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photonics

If there is one thing that doesn’t go well with photonics circuits it is straight corners. The FLX can print any feature without design rule restrictions: circles, non-orthogonal shapes, lines and curves. At any width, any spacing and in any orientation, stretched over large areas. All of these can be combined in the same layer if necessary, at the highest resolution with the best CD control and without loss of writing speed. This is ideal for photonics devices, especially those including sub-wavelength features.

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mask cost reduction

In 300 mm foundries the vast majority of IC designs need fewer than 1,000 wafers. At 40/45 nm nodes and below, soaring mask costs claim a significant chunk of the total budget. In a typical 40-piece mask set, just four advanced phase-shift immersion masks account for one third of the set cost. The FLX-series is compatible with immersion lithography but doesn’t require such masks to be manufactured. This is an immediate cost saver.

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via rom

Once a logic IC design gains some level of complexity it often includes a microprocessor unit for on-chip housekeeping tasks. Microprocessors need software to run. If you don’t want the complexity of an external non-volatile memory, you have the choice between embedded Flash and Via ROM. Via ROM requires an immersion mask and embedded Flash is not available at the most advanced nodes. Therefore many designs stay in 40/45 nm. Without the associated mask cost Mapper offers a new kind of Via ROM without worries that it will be costly to change the programming in a new revision. This allows designs to migrate to the more advanced nodes.

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nvram capacity increase

If you need a local density increase in an existing design you could look out for a more advanced foundry. However, your design might not need the whole package that a 40/45 nm foundry process comes with. Full node shrink implies new material stacks, different thicknesses and a myriad of design rules. Alternatively, you can use the FLX series to provide you with enhanced resolution while keeping the rest of the process untouched. For example, for increasing the NVRAM capacity in a 130 nm device, copper interconnects are not required. The FLX system helps to achieve this without complex OPC schemes, without changes to your processing line and at a low barrier to adoption.

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anti-counterfeiting and traceability

Miniscule Mapper-made truly unique IC’s with short range RF functionality can function as an effective anti-counterfeiting security feature. Not only for medicines and high-value consumer products, such as liquors, perfumes and fashion bags. But due to the low added manufacturing cost such IC’s are also suitable for embedding in everyday goods.

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long tail and industry 4.0

Many foundries are hesitant to accept orders for fewer than 100 wafers. The average IC measures 10 mm2, therefore 100 wafers yield 500,000 IC's. Many industrial and consumer products don’t need that many. In the meantime, Industry 4.0 envisions fast adaptation to increasingly segmented markets. This requires short design cycles and small product series. At advanced technology nodes, increasing startup costs have moved IC design and manufacturing in exactly the opposite direction. By reducing startup costs and cycle time, Mapper’s e-beam for manufacturing introduces Industry 4.0 into the semiconductor industry.

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layer reduction in advanced nodes

Making 28 nm logic devices using 193 nm excimer lasers comes with a trade-off: Rayleigh’s limit (k1λ/NA) forces IC designs into increasingly regularized and one-dimensional layouts. The indirect cost of low-k1 manufacturing is a layer count increase and a compromised design for library and custom cells. E-beam writing doesn’t suffer from diffraction limits and prints unrestricted, full 2D, patterns while matching the same resolution as the best optical methods. This opens new ways for complexity and cost reductions in 28 nm nodes and below. Spurious metal layers can be eliminated and multiple-exposure schemes revisited.

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large field applications

E-beam patterns are generated on the fly from a computer memory and not from a mask. Such patterns don’t confine themselves to a physical field size. With simple memory expansions larger field sizes than 26x33mm2 become a breeze and eliminate the need for complex stitching schemes. Large field image sensors are typical applications. Depending on the specifics of the application, even full-wafer designs can be considered, as every pixel on the wafer is individually addressable.